fixed class member append hang, additional rizin architectures
JoYo
parent
e0c42b8406
commit
1de3ddb8d8
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@ -54,50 +54,72 @@ class _CapstoneBase:
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def __lt__(self, other):
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return len(self) < len(other)
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def __contains__(self, name: str):
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return hasattr(self, name)
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@property
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def objdump(self) -> str:
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opcodes = str()
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if "_objdump" in self:
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return self._objdump
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_objdump = str()
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for opcode in self.disassembly:
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opcodes += f"{opcode.address:#02x}:\t{opcode.mnemonic}\t{opcode.op_str}\n"
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_objdump += f"{opcode.address:#02x}:\t{opcode.mnemonic}\t{opcode.op_str}\n"
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return opcodes
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self._objdump = _objdump
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return self._objdump
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@property
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def disasm(self) -> list:
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opcodes = list()
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if "_disasm" in self:
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return self._disasm
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_disasm = list()
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for opcode in self.disassembly:
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opcodes.append([opcode.address, opcode.mnemonic, opcode.op_str])
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if not "unknown" == opcode.mnemonic:
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_disasm.append([opcode.address, opcode.mnemonic, opcode.op_str])
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return opcodes
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self._disasm = _disasm
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return self._disasm
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@property
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def rets(self) -> list:
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if hasattr(self, "_rets"):
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if "_rets" in self:
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return self._rets
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self._rets = list()
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_rets = list()
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for opcode in self.disassembly:
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if "ret" in opcode.mnemonic:
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self._rets.append(opcode.mnemonic)
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_rets.append(opcode.mnemonic)
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self._rets = _rets
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return self._rets
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@property
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def ret_rates(self) -> list:
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if "_ret_rates" in self:
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return self._ret_rates
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rates = dict()
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for mnemonic in set(self.rets):
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rates[mnemonic] = self.rets.count(mnemonic)
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listed = sorted(((value, key) for (key, value) in rates.items()), reverse=True)
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_ret_rates = sorted(
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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return listed
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self._ret_rates = _ret_rates
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return self._ret_rates
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@property
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def mnemonic_rates(self) -> list:
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if "_mnemonic_rates" in self:
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return self._mnemonic_rates
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mnemonics = list()
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for opcode in self.disassembly:
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@ -108,9 +130,12 @@ class _CapstoneBase:
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for mnemonic in set(mnemonics):
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rates[mnemonic] = mnemonics.count(mnemonic)
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listed = sorted(((value, key) for (key, value) in rates.items()), reverse=True)
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_mnemonic_rates = sorted(
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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return listed
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self._mnemonic_rates = _mnemonic_rates
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return self._mnemonic_rates
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class x86_16(_CapstoneBase):
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@ -20,31 +20,36 @@ class _RizinBase:
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return self.objdump
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def __len__(self) -> int:
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return len(self.disassembly)
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return len(self.disasm)
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def __lt__(self, other):
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return len(self) < len(other)
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def __contains__(self, name: str):
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return hasattr(self, name)
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@property
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def objdump(self) -> str:
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if hasattr(self, "_objdump"):
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if "_objdump" in self:
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return self._objdump
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self._objdump = str()
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_objdump = str()
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for each in self.disassembly:
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offset = each.get("offset")
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opcode = each.get("opcode")
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self._objdump += f"{offset:#02x}:\t{opcode}\n"
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if opcode:
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_objdump += f"{offset:#02x}:\t{opcode}\n"
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self._objdump = _objdump
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return self._objdump
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@property
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def disasm(self) -> list:
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if hasattr(self, "_disasm"):
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if "_disasm" in self:
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return self._disasm
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self._disasm = list()
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_disasm = list()
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for each in self.disassembly:
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offset = each.get("offset")
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@ -53,30 +58,32 @@ class _RizinBase:
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if opcode:
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mnemonic = opcode.split(" ")[0]
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opcode = opcode.split(" ")[1:]
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else:
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mnemonic = None
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self._disasm.append([offset, mnemonic, opcode])
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_disasm.append([offset, mnemonic, opcode])
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self._disasm = _disasm
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return self._disasm
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@property
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def rets(self) -> list:
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if hasattr(self, "_rets"):
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if "_rets" in self:
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return self._rets
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self._rets = list()
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_rets = list()
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for each in self.disasm:
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_, mnemonic, _ = each
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if mnemonic and "ret" in mnemonic:
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self._rets.append(mnemonic)
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_rets.append(mnemonic)
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self._rets = _rets
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return self._rets
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@property
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def ret_rates(self) -> list:
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if "_ret_rates" in self:
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return self._ret_rates
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rates = dict()
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for mnemonic in set(self.rets):
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@ -86,10 +93,14 @@ class _RizinBase:
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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return _ret_rates
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self._ret_rates = _ret_rates
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return self._ret_rates
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@property
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def mnemonic_rates(self) -> list:
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if "_mnemonic_rates" in self:
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return self._mnemonic_rates
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mnemonics = list()
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for each in self.disasm:
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@ -107,8 +118,102 @@ class _RizinBase:
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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return _mnemonic_rates
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self._mnemonic_rates = _mnemonic_rates
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return self._mnemonic_rates
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class _6502_8(_RizinBase):
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arch_cmds = ["e asm.arch=6502", "e asm.bits=8"]
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name = "6502/NES/C64/Tamagotchi/T-1000 CPU"
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class _6502_16(_RizinBase):
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arch_cmds = ["e asm.arch=6502", "e asm.bits=16"]
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name = "6502/NES/C64/Tamagotchi/T-1000 CPU"
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class _8051(_RizinBase):
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arch_cmds = ["e asm.arch=8051", "e asm.bits=8"]
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name = "8051 Intel CPU"
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class amd29k(_RizinBase):
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arch_cmds = ["e asm.arch=amd29k", "e asm.bits=32"]
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name = "AMD 29k RISC CPU"
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class arc_16(_RizinBase):
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arch_cmds = ["e asm.arch=arc", "e asm.bits=16"]
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name = "Argonaut RISC Core"
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class arc_32(_RizinBase):
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arch_cmds = ["e asm.arch=arc", "e asm.bits=32"]
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name = "Argonaut RISC Core"
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class arm_as_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm.as", "e asm.bits=16"]
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name = "as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)"
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class arm_as_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm.as", "e asm.bits=32"]
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name = "as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)"
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class arm_as_64(_RizinBase):
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arch_cmds = ["e asm.arch=arm.as", "e asm.bits=64"]
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name = "as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)"
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class arm_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm", "e asm.bits=16"]
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name = "Capstone ARM disassembler"
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class arm_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm", "e asm.bits=32"]
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name = "Capstone ARM disassembler"
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class arm_64(_RizinBase):
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arch_cmds = ["e asm.arch=arm", "e asm.bits=64"]
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name = "Capstone ARM disassembler"
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class arm_gnu_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=16"]
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name = "Acorn RISC Machine CPU"
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class arm_gnu_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=32"]
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name = "Acorn RISC Machine CPU"
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class arm_gnu_64(_RizinBase):
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arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=64"]
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name = "Acorn RISC Machine CPU"
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class arm_wine_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=16"]
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name = "WineDBG's ARM disassembler"
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class arm_wine_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=32"]
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name = "WineDBG's ARM disassembler"
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class x86_16(_RizinBase):
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arch_cmds = ["e asm.arch=x86", "e asm.bits=16"]
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class x86_32(_RizinBase):
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arch_cmds = ["e asm.arch=x86", "e asm.bits=32"]
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class x86_64(_RizinBase):
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arch_cmds = ["e asm.arch=x86", "e asm.bits=64"]
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@ -111,7 +111,26 @@ def subdisassem_script():
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session.commit()
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rizin_archs = [
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rizin_wrapper._6502_8,
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rizin_wrapper._6502_16,
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rizin_wrapper._8051,
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rizin_wrapper.amd29k,
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rizin_wrapper.arc_16,
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rizin_wrapper.arc_32,
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rizin_wrapper.arm_as_16,
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rizin_wrapper.arm_as_32,
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rizin_wrapper.arm_as_64,
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rizin_wrapper.arm_16,
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rizin_wrapper.arm_32,
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rizin_wrapper.arm_64,
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rizin_wrapper.arm_gnu_16,
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rizin_wrapper.arm_gnu_32,
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rizin_wrapper.arm_gnu_64,
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rizin_wrapper.arm_wine_16,
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rizin_wrapper.arm_wine_32,
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rizin_wrapper.x86_16,
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rizin_wrapper.x86_32,
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rizin_wrapper.x86_64,
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]
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for arch in rizin_archs:
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