checking for unessisary disassembly
parent
c4bde9632a
commit
b64d04dc3a
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@ -30,20 +30,42 @@ import logging
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class _CapstoneBase:
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def __init__(self, payload: bytes, offset: int = 0):
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self.disassembly = list()
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for opcode in self.capstone.disasm(payload, offset):
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self.disassembly.append(opcode)
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def __init__(self):
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self.arch = self.__class__.__name__
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pass
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def __repr__(self) -> str:
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return self.objdump
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def __len__(self) -> int:
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if not self.disassembly:
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logging.debug(
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f"payload_missing: use {self.__class__}.load(payload=bytes) prior"
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)
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return 0
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return len(self.disassembly)
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def load(self, payload: bytes, offset: int = 0):
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disassembly = list()
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for opcode in self.capstone.disasm(payload, offset):
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disassembly.append(opcode)
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if disassembly:
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self.disassembly = disassembly
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else:
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logging.debug("disassembly_empty")
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self.disassembly = list()
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@property
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def objdump(self) -> str:
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if not self.disassembly:
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logging.debug(
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f"payload_missing: use {self.__class__}.load(payload=bytes) prior"
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)
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return ""
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opcodes = str()
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for opcode in self.disassembly:
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@ -53,6 +75,12 @@ class _CapstoneBase:
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@property
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def disasm(self) -> list:
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if not self.disassembly:
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logging.debug(
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f"payload_missing: use {self.__class__}.load(payload=bytes) prior"
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)
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return []
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opcodes = list()
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for opcode in self.disassembly:
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@ -70,64 +98,51 @@ class _CapstoneBase:
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class X86_intel(_CapstoneBase):
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capstone = Cs(CS_ARCH_X86, CS_MODE_16)
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arch = "x86-16"
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class X86(_CapstoneBase):
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capstone = Cs(CS_ARCH_X86, CS_MODE_32)
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arch = "x86-32"
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class X86_64(_CapstoneBase):
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capstone = Cs(CS_ARCH_X86, CS_MODE_64)
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arch = "x86-64"
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class ARM(_CapstoneBase):
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capstone = Cs(CS_ARCH_ARM, CS_MODE_ARM)
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arch = "ARM"
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class Thumb(_CapstoneBase):
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capstone = Cs(CS_ARCH_ARM, CS_MODE_THUMB)
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arch = "Thumb"
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class ARM_64(_CapstoneBase):
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capstone = Cs(CS_ARCH_ARM64, CS_MODE_ARM)
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arch = "ARM 64"
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class MIPS_32_eb(_CapstoneBase):
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capstone = Cs(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN)
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arch = "MIPS-32 (Big-endian)"
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class MIPS_64_el(_CapstoneBase):
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capstone = Cs(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN)
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arch = "MIPS-64-EL (Little-endian)"
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class PPC_64(_CapstoneBase):
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capstone = Cs(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN)
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arch = "PPC-64"
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class Sparc(_CapstoneBase):
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capstone = Cs(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN)
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arch = "Sparc"
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class SparcV9(_CapstoneBase):
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capstone = Cs(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9)
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arch = "SparcV9"
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class SystemZ(_CapstoneBase):
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capstone = Cs(CS_ARCH_SYSZ, 0)
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arch = "SystemZ"
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class XCore(_CapstoneBase):
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capstone = Cs(CS_ARCH_XCORE, 0)
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arch = "XCore"
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@ -33,12 +33,11 @@ class Disassembly(Base):
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@property
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def values(self) -> dict:
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values_dict = {
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"id": self.id,
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"arch": self.arch,
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"checksum": self.checksum,
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"count": self.count,
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"size": self.size,
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"offset": self.offset,
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"path": self.path,
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}
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return values_dict
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@ -89,7 +89,22 @@ def subdisassem_script():
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for arch in archs:
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for offset in range(args.fuzz):
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disasembler = arch(payload=raw_bytes, offset=offset)
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disasembler = arch()
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exists = (
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session.query(Disassembly)
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.filter(Disassembly.checksum == checksum)
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.filter(Disassembly.offset == offset)
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.filter(Disassembly.arch == disasembler.arch)
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.first()
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)
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if exists:
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logging.debug(
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f"subdiassembly_exists: {[disasembler.arch, checksum, offset]}"
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)
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continue
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disasembler.load(payload=raw_bytes, offset=offset)
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row = Disassembly()
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row.arch = disasembler.arch
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row.checksum = checksum
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@ -98,16 +113,6 @@ def subdisassem_script():
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row.offset = offset
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row.opcodes = disasembler.objdump
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row.path = str(args.bin_path.absolute())
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exists = (
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session.query(Disassembly)
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.filter(Disassembly.checksum == row.checksum)
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.filter(Disassembly.offset == row.offset)
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.filter(Disassembly.arch == row.arch)
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.first()
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)
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if not exists:
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session.add(row)
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session.commit()
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