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d656d97818
...
e0c42b8406
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@ -54,72 +54,50 @@ class _CapstoneBase:
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def __lt__(self, other):
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return len(self) < len(other)
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def __contains__(self, name: str):
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return hasattr(self, name)
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@property
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def objdump(self) -> str:
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if "_objdump" in self:
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return self._objdump
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_objdump = str()
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opcodes = str()
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for opcode in self.disassembly:
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_objdump += f"{opcode.address:#02x}:\t{opcode.mnemonic}\t{opcode.op_str}\n"
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opcodes += f"{opcode.address:#02x}:\t{opcode.mnemonic}\t{opcode.op_str}\n"
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self._objdump = _objdump
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return self._objdump
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return opcodes
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@property
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def disasm(self) -> list:
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if "_disasm" in self:
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return self._disasm
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_disasm = list()
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opcodes = list()
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for opcode in self.disassembly:
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if not "unknown" == opcode.mnemonic:
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_disasm.append([opcode.address, opcode.mnemonic, opcode.op_str])
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opcodes.append([opcode.address, opcode.mnemonic, opcode.op_str])
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self._disasm = _disasm
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return self._disasm
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return opcodes
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@property
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def rets(self) -> list:
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if "_rets" in self:
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if hasattr(self, "_rets"):
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return self._rets
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_rets = list()
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self._rets = list()
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for opcode in self.disassembly:
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if "ret" in opcode.mnemonic:
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_rets.append(opcode.mnemonic)
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self._rets.append(opcode.mnemonic)
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self._rets = _rets
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return self._rets
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@property
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def ret_rates(self) -> list:
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if "_ret_rates" in self:
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return self._ret_rates
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rates = dict()
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for mnemonic in set(self.rets):
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rates[mnemonic] = self.rets.count(mnemonic)
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_ret_rates = sorted(
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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listed = sorted(((value, key) for (key, value) in rates.items()), reverse=True)
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self._ret_rates = _ret_rates
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return self._ret_rates
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return listed
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@property
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def mnemonic_rates(self) -> list:
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if "_mnemonic_rates" in self:
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return self._mnemonic_rates
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mnemonics = list()
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for opcode in self.disassembly:
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@ -130,12 +108,9 @@ class _CapstoneBase:
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for mnemonic in set(mnemonics):
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rates[mnemonic] = mnemonics.count(mnemonic)
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_mnemonic_rates = sorted(
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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listed = sorted(((value, key) for (key, value) in rates.items()), reverse=True)
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self._mnemonic_rates = _mnemonic_rates
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return self._mnemonic_rates
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return listed
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class x86_16(_CapstoneBase):
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@ -20,36 +20,31 @@ class _RizinBase:
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return self.objdump
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def __len__(self) -> int:
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return len(self.disasm)
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return len(self.disassembly)
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def __lt__(self, other):
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return len(self) < len(other)
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def __contains__(self, name: str):
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return hasattr(self, name)
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@property
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def objdump(self) -> str:
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if "_objdump" in self:
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if hasattr(self, "_objdump"):
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return self._objdump
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_objdump = str()
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self._objdump = str()
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for each in self.disassembly:
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offset = each.get("offset")
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opcode = each.get("opcode")
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if opcode:
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_objdump += f"{offset:#02x}:\t{opcode}\n"
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self._objdump += f"{offset:#02x}:\t{opcode}\n"
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self._objdump = _objdump
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return self._objdump
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@property
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def disasm(self) -> list:
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if "_disasm" in self:
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if hasattr(self, "_disasm"):
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return self._disasm
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_disasm = list()
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self._disasm = list()
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for each in self.disassembly:
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offset = each.get("offset")
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@ -58,32 +53,30 @@ class _RizinBase:
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if opcode:
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mnemonic = opcode.split(" ")[0]
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opcode = opcode.split(" ")[1:]
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_disasm.append([offset, mnemonic, opcode])
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else:
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mnemonic = None
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self._disasm.append([offset, mnemonic, opcode])
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self._disasm = _disasm
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return self._disasm
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@property
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def rets(self) -> list:
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if "_rets" in self:
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if hasattr(self, "_rets"):
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return self._rets
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_rets = list()
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self._rets = list()
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for each in self.disasm:
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_, mnemonic, _ = each
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if mnemonic and "ret" in mnemonic:
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_rets.append(mnemonic)
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self._rets.append(mnemonic)
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self._rets = _rets
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return self._rets
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@property
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def ret_rates(self) -> list:
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if "_ret_rates" in self:
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return self._ret_rates
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rates = dict()
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for mnemonic in set(self.rets):
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@ -93,14 +86,10 @@ class _RizinBase:
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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self._ret_rates = _ret_rates
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return self._ret_rates
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return _ret_rates
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@property
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def mnemonic_rates(self) -> list:
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if "_mnemonic_rates" in self:
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return self._mnemonic_rates
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mnemonics = list()
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for each in self.disasm:
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@ -118,417 +107,8 @@ class _RizinBase:
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((value, key) for (key, value) in rates.items()), reverse=True
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)
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self._mnemonic_rates = _mnemonic_rates
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return self._mnemonic_rates
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class _6502_8(_RizinBase):
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arch_cmds = ["e asm.arch=6502", "e asm.bits=8"]
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class _6502_16(_RizinBase):
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arch_cmds = ["e asm.arch=6502", "e asm.bits=16"]
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class _8051(_RizinBase):
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arch_cmds = ["e asm.arch=8051", "e asm.bits=8"]
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class amd29k(_RizinBase):
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arch_cmds = ["e asm.arch=amd29k", "e asm.bits=32"]
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class arc_16(_RizinBase):
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arch_cmds = ["e asm.arch=arc", "e asm.bits=16"]
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class arc_32(_RizinBase):
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arch_cmds = ["e asm.arch=arc", "e asm.bits=32"]
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class arm_as_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm.as", "e asm.bits=16"]
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class arm_as_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm.as", "e asm.bits=32"]
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class arm_as_64(_RizinBase):
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arch_cmds = ["e asm.arch=arm.as", "e asm.bits=64"]
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class arm_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm", "e asm.bits=16"]
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class arm_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm", "e asm.bits=32"]
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class arm_64(_RizinBase):
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arch_cmds = ["e asm.arch=arm", "e asm.bits=64"]
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class arm_gnu_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=16"]
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class arm_gnu_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=32"]
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class arm_gnu_64(_RizinBase):
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arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=64"]
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class arm_wine_16(_RizinBase):
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arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=16"]
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class arm_wine_32(_RizinBase):
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arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=32"]
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class avr_8(_RizinBase):
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arch_cmds = ["e asm.arch=avr", "e asm.bits=8"]
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class avr_16(_RizinBase):
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arch_cmds = ["e asm.arch=avr", "e asm.bits=16"]
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class bf_16(_RizinBase):
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arch_cmds = ["e asm.arch=bf", "e asm.bits=16"]
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class bf_32(_RizinBase):
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arch_cmds = ["e asm.arch=bf", "e asm.bits=32"]
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class bf_64(_RizinBase):
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arch_cmds = ["e asm.arch=bf", "e asm.bits=64"]
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class bf_64(_RizinBase):
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arch_cmds = ["e asm.arch=bf", "e asm.bits=64"]
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class chip8(_RizinBase):
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arch_cmds = ["e asm.arch=chip8", "e asm.bits=32"]
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class cr_16(_RizinBase):
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arch_cmds = ["e asm.arch=cr16", "e asm.bits=16"]
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class cris(_RizinBase):
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arch_cmds = ["e asm.arch=cris", "e asm.bits=32"]
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class dalvik_32(_RizinBase):
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arch_cmds = ["e asm.arch=dalvik", "e asm.bits=32"]
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class dalvik_64(_RizinBase):
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arch_cmds = ["e asm.arch=dalvik", "e asm.bits=64"]
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class dcpu16(_RizinBase):
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arch_cmds = ["e asm.arch=dcpu16", "e asm.bits=16"]
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class ebc_32(_RizinBase):
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arch_cmds = ["e asm.arch=ebc", "e asm.bits=32"]
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class ebc_64(_RizinBase):
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arch_cmds = ["e asm.arch=ebc", "e asm.bits=64"]
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class gb(_RizinBase):
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arch_cmds = ["e asm.arch=gb", "e asm.bits=16"]
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class h8300(_RizinBase):
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arch_cmds = ["e asm.arch=h8300", "e asm.bits=16"]
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class hexagon(_RizinBase):
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arch_cmds = ["e asm.arch=hexagon", "e asm.bits=32"]
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class hppa(_RizinBase):
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arch_cmds = ["e asm.arch=hppa", "e asm.bits=32"]
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class i4004(_RizinBase):
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arch_cmds = ["e asm.arch=i4004", "e asm.bits=4"]
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class i8080(_RizinBase):
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arch_cmds = ["e asm.arch=i8080", "e asm.bits=8"]
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class java(_RizinBase):
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arch_cmds = ["e asm.arch=java", "e asm.bits=32"]
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class lanai(_RizinBase):
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arch_cmds = ["e asm.arch=lanai", "e asm.bits=32"]
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class lh5801(_RizinBase):
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arch_cmds = ["e asm.arch=lh5801", "e asm.bits=8"]
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class lm32(_RizinBase):
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arch_cmds = ["e asm.arch=lm32", "e asm.bits=32"]
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class luac(_RizinBase):
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arch_cmds = ["e asm.arch=luac", "e asm.bits=8"]
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class m68k(_RizinBase):
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arch_cmds = ["e asm.arch=m68k", "e asm.bits=32"]
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class m680x_8(_RizinBase):
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arch_cmds = ["e asm.arch=m680x", "e asm.bits=8"]
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class m680x_32(_RizinBase):
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arch_cmds = ["e asm.arch=m680x", "e asm.bits=32"]
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class malbolge(_RizinBase):
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arch_cmds = ["e asm.arch=malbolge", "e asm.bits=32"]
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class mcore(_RizinBase):
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arch_cmds = ["e asm.arch=mcore", "e asm.bits=32"]
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class mcs96(_RizinBase):
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arch_cmds = ["e asm.arch=mcs96", "e asm.bits=16"]
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class mips_16(_RizinBase):
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arch_cmds = ["e asm.arch=mips", "e asm.bits=16"]
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class mips_32(_RizinBase):
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arch_cmds = ["e asm.arch=mips", "e asm.bits=32"]
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class mips_64(_RizinBase):
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arch_cmds = ["e asm.arch=mips", "e asm.bits=64"]
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class mips_gnu_32(_RizinBase):
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arch_cmds = ["e asm.arch=mips.gnu", "e asm.bits=32"]
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class mips_gnu_64(_RizinBase):
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arch_cmds = ["e asm.arch=mips.gnu", "e asm.bits=64"]
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class msp430(_RizinBase):
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arch_cmds = ["e asm.arch=msp430", "e asm.bits=16"]
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class nios2(_RizinBase):
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arch_cmds = ["e asm.arch=nios2", "e asm.bits=32"]
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class or1k(_RizinBase):
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arch_cmds = ["e asm.arch=or1k", "e asm.bits=32"]
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class pic(_RizinBase):
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arch_cmds = ["e asm.arch=pic", "e asm.bits=8"]
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class ppc_as_32(_RizinBase):
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arch_cmds = ["e asm.arch=ppc.as", "e asm.bits=32"]
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class ppc_as_64(_RizinBase):
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arch_cmds = ["e asm.arch=ppc.as", "e asm.bits=64"]
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class ppc_32(_RizinBase):
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arch_cmds = ["e asm.arch=ppc", "e asm.bits=32"]
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class ppc_64(_RizinBase):
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arch_cmds = ["e asm.arch=ppc", "e asm.bits=64"]
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class ppc_gnu_32(_RizinBase):
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arch_cmds = ["e asm.arch=ppc.gnu", "e asm.bits=32"]
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class ppc_gnu_64(_RizinBase):
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arch_cmds = ["e asm.arch=ppc.gnu", "e asm.bits=64"]
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class propeller(_RizinBase):
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arch_cmds = ["e asm.arch=propeller", "e asm.bits=32"]
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class pyc_8(_RizinBase):
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arch_cmds = ["e asm.arch=pyc", "e asm.bits=8"]
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class pyc_16(_RizinBase):
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arch_cmds = ["e asm.arch=pyc", "e asm.bits=16"]
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class riscv_32(_RizinBase):
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arch_cmds = ["e asm.arch=riscv", "e asm.bits=32"]
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class riscv_64(_RizinBase):
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arch_cmds = ["e asm.arch=riscv", "e asm.bits=64"]
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class rsp(_RizinBase):
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arch_cmds = ["e asm.arch=rsp", "e asm.bits=32"]
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class sh(_RizinBase):
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arch_cmds = ["e asm.arch=sh", "e asm.bits=32"]
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class snes_8(_RizinBase):
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arch_cmds = ["e asm.arch=snes", "e asm.bits=8"]
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class snes_16(_RizinBase):
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arch_cmds = ["e asm.arch=snes", "e asm.bits=16"]
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class sparc_32(_RizinBase):
|
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arch_cmds = ["e asm.arch=sparc", "e asm.bits=32"]
|
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||||
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||||
class sparc_64(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=sparc", "e asm.bits=64"]
|
||||
|
||||
|
||||
class sparc_gnu_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=sparc.gnu", "e asm.bits=32"]
|
||||
|
||||
|
||||
class sparc_gnu_64(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=sparc.gnu", "e asm.bits=64"]
|
||||
|
||||
|
||||
class spc700(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=spc700", "e asm.bits=16"]
|
||||
|
||||
|
||||
class sysz_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=sysz", "e asm.bits=32"]
|
||||
|
||||
|
||||
class sysz_64(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=sysz", "e asm.bits=64"]
|
||||
|
||||
|
||||
class tms320(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=tms320", "e asm.bits=32"]
|
||||
|
||||
|
||||
class tms320c64x(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=tms320c64x", "e asm.bits=32"]
|
||||
|
||||
|
||||
class tricore(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=tricore", "e asm.bits=32"]
|
||||
|
||||
|
||||
class v810_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=v810", "e asm.bits=32"]
|
||||
|
||||
|
||||
class v850(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=v850", "e asm.bits=32"]
|
||||
|
||||
|
||||
class vax_8(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=vax", "e asm.bits=8"]
|
||||
|
||||
|
||||
class vax_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=vax", "e asm.bits=32"]
|
||||
|
||||
|
||||
class wasm_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=wasm", "e asm.bits=32"]
|
||||
|
||||
|
||||
class x86_as_16(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.as", "e asm.bits=16"]
|
||||
|
||||
|
||||
class x86_as_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.as", "e asm.bits=32"]
|
||||
|
||||
|
||||
class x86_as_64(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.as", "e asm.bits=64"]
|
||||
return _mnemonic_rates
|
||||
|
||||
|
||||
class x86_16(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86", "e asm.bits=16"]
|
||||
|
||||
|
||||
class x86_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86", "e asm.bits=32"]
|
||||
|
||||
|
||||
class x86_64(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86", "e asm.bits=64"]
|
||||
|
||||
|
||||
class x86_nasm_16(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=16"]
|
||||
|
||||
|
||||
class x86_nasm_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=32"]
|
||||
|
||||
|
||||
class x86_nasm_64(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=64"]
|
||||
|
||||
|
||||
class x86_nz_16(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=16"]
|
||||
|
||||
|
||||
class x86_nz_32(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=32"]
|
||||
|
||||
|
||||
class x86_nz_64(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=64"]
|
||||
|
||||
|
||||
class xap(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=xap", "e asm.bits=16"]
|
||||
|
||||
|
||||
class xcore(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=xcore", "e asm.bits=32"]
|
||||
|
||||
|
||||
class xtensa(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=xtensa", "e asm.bits=32"]
|
||||
|
||||
|
||||
class z80(_RizinBase):
|
||||
arch_cmds = ["e asm.arch=z80", "e asm.bits=8"]
|
||||
|
|
|
|||
|
|
@ -111,109 +111,7 @@ def subdisassem_script():
|
|||
session.commit()
|
||||
|
||||
rizin_archs = [
|
||||
rizin_wrapper._6502_8,
|
||||
rizin_wrapper._6502_16,
|
||||
rizin_wrapper._8051,
|
||||
rizin_wrapper.amd29k,
|
||||
rizin_wrapper.arc_16,
|
||||
rizin_wrapper.arc_32,
|
||||
rizin_wrapper.arm_as_16,
|
||||
rizin_wrapper.arm_as_32,
|
||||
rizin_wrapper.arm_as_64,
|
||||
rizin_wrapper.arm_16,
|
||||
rizin_wrapper.arm_32,
|
||||
rizin_wrapper.arm_64,
|
||||
rizin_wrapper.arm_gnu_16,
|
||||
rizin_wrapper.arm_gnu_32,
|
||||
rizin_wrapper.arm_gnu_64,
|
||||
rizin_wrapper.arm_wine_16,
|
||||
rizin_wrapper.arm_wine_32,
|
||||
rizin_wrapper.avr_8,
|
||||
rizin_wrapper.avr_16,
|
||||
rizin_wrapper.bf_16,
|
||||
rizin_wrapper.bf_32,
|
||||
rizin_wrapper.bf_64,
|
||||
rizin_wrapper.bf_64,
|
||||
rizin_wrapper.chip8,
|
||||
rizin_wrapper.cr_16,
|
||||
rizin_wrapper.cris,
|
||||
rizin_wrapper.dalvik_32,
|
||||
rizin_wrapper.dalvik_64,
|
||||
rizin_wrapper.dcpu16,
|
||||
rizin_wrapper.ebc_32,
|
||||
rizin_wrapper.ebc_64,
|
||||
rizin_wrapper.gb,
|
||||
rizin_wrapper.h8300,
|
||||
rizin_wrapper.hexagon,
|
||||
rizin_wrapper.hppa,
|
||||
rizin_wrapper.i4004,
|
||||
rizin_wrapper.i8080,
|
||||
rizin_wrapper.java,
|
||||
rizin_wrapper.lanai,
|
||||
rizin_wrapper.lh5801,
|
||||
rizin_wrapper.lm32,
|
||||
rizin_wrapper.luac,
|
||||
rizin_wrapper.m68k,
|
||||
rizin_wrapper.m680x_8,
|
||||
rizin_wrapper.m680x_32,
|
||||
rizin_wrapper.malbolge,
|
||||
rizin_wrapper.mcore,
|
||||
rizin_wrapper.mcs96,
|
||||
rizin_wrapper.mips_16,
|
||||
rizin_wrapper.mips_32,
|
||||
rizin_wrapper.mips_64,
|
||||
rizin_wrapper.mips_gnu_32,
|
||||
rizin_wrapper.mips_gnu_64,
|
||||
rizin_wrapper.msp430,
|
||||
rizin_wrapper.nios2,
|
||||
rizin_wrapper.or1k,
|
||||
rizin_wrapper.pic,
|
||||
rizin_wrapper.ppc_as_32,
|
||||
rizin_wrapper.ppc_as_64,
|
||||
rizin_wrapper.ppc_32,
|
||||
rizin_wrapper.ppc_64,
|
||||
rizin_wrapper.ppc_gnu_32,
|
||||
rizin_wrapper.ppc_gnu_64,
|
||||
rizin_wrapper.propeller,
|
||||
rizin_wrapper.pyc_8,
|
||||
rizin_wrapper.pyc_16,
|
||||
rizin_wrapper.riscv_32,
|
||||
rizin_wrapper.riscv_64,
|
||||
rizin_wrapper.rsp,
|
||||
rizin_wrapper.sh,
|
||||
rizin_wrapper.snes_8,
|
||||
rizin_wrapper.snes_16,
|
||||
rizin_wrapper.sparc_32,
|
||||
rizin_wrapper.sparc_64,
|
||||
rizin_wrapper.sparc_gnu_32,
|
||||
rizin_wrapper.sparc_gnu_64,
|
||||
rizin_wrapper.spc700,
|
||||
rizin_wrapper.sysz_32,
|
||||
rizin_wrapper.sysz_64,
|
||||
rizin_wrapper.tms320,
|
||||
rizin_wrapper.tms320c64x,
|
||||
rizin_wrapper.tricore,
|
||||
rizin_wrapper.v810_32,
|
||||
rizin_wrapper.v850,
|
||||
rizin_wrapper.vax_8,
|
||||
rizin_wrapper.vax_32,
|
||||
rizin_wrapper.wasm_32,
|
||||
rizin_wrapper.x86_as_16,
|
||||
rizin_wrapper.x86_as_32,
|
||||
rizin_wrapper.x86_as_64,
|
||||
rizin_wrapper.x86_16,
|
||||
rizin_wrapper.x86_32,
|
||||
rizin_wrapper.x86_64,
|
||||
rizin_wrapper.x86_nasm_16,
|
||||
rizin_wrapper.x86_nasm_32,
|
||||
rizin_wrapper.x86_nasm_64,
|
||||
rizin_wrapper.x86_nz_16,
|
||||
rizin_wrapper.x86_nz_32,
|
||||
rizin_wrapper.x86_nz_64,
|
||||
rizin_wrapper.xap,
|
||||
rizin_wrapper.xcore,
|
||||
rizin_wrapper.xtensa,
|
||||
rizin_wrapper.z80,
|
||||
]
|
||||
|
||||
for arch in rizin_archs:
|
||||
|
|
|
|||
Loading…
Reference in New Issue